With respect to a semiconductor device using silicon carbide on the uppermost layer of a semiconductor substrate and to a method of manufacturing the same, as described in the following, there have been a number of publications and disclosures of inventions, but in the prior art, a semiconductor device using a silicon carbide substrate has a structure in which a gate electrode is normally formed on the (0001) face. In this case, when forming a p type or n type region by ion implantation in the (0001) face, ion implantation of a p type or n type impurity is followed by heat treatment at a high temperature of 1500° C. or above for activation, so silicon evaporates from the silicon carbide surface, leading to increased roughness of the silicon carbide surface. This results in reduced channel mobility of metal-insulation film-semiconductor field-effect transistors (MISFETs) or metal-semiconductor field-effect transistors (MESFETs), and increased leak current in Schottky barrier diodes (SBDs) and junction type field-effect transistors (JFETs) caused by larger crystal defects in the ion implantation region, problems which make practical use impossible.
For example, Non-Patent Document 1 describes the occurrence of step punching due to high-temperature heat treatment for impurity activation, producing increased surface roughness, so that in order to reduce the On-resistance value of a 4H—SiC power MOSFET to the theoretical value, the channel mobility was no more than 1 cm2/Vs, even though 100 cm2/Vs or more is needed.
[Non-Patent Document 1]: J. A. Cooper, Jr., M. R. Melloch, R. Singh, A. Agarwal, J. W. Palmour, IEEE Transaction on electron devices, vol. 49, No. 4, April 2002, p. 658
Also, Non-Patent Document 2 describes a DiMOSFET type SiC power MOSFET in which channel mobility at room temperature was only 22 cm2/Vs, due to the use of heat treatment in the region of 1600° C. following ion implantation of a p type impurity (aluminum).
[Non-Patent Document 2]: S. H. Ryu, A. Agarwal, J. Richmond, J. Palmour, N. Saks and J. Williams, IEEE Electron device letters, vol. 23, No. 6, Jun. 2002, p. 321
Also, Non-Patent Document 3 describes a lateral DMOSFET type SiC power MOSFET in which channel mobility was only 4 to 5 cm2/Vs, due to the use of activation heat treatment at 1600° C. for 40 minutes following ion implantation of a p type impurity (aluminum).
[Non-Patent Document 3]: J. Spitz, M. R. Melloch, J. A. Cooper, Jr., M. A Capano, IEEE Electron device letters, vol. 19, No. 4, April 1998, p. 100